Very Large Scale Integration (VLSI) Design

This comprehensive VLSI design course covers the entire semiconductor design lifecycle, bridging the gap between theoretical electronics and real-world chip manufacturing. You will start by mastering Digital Logic and Hardware Description Languages (Verilog), learning to code complex systems at the Register Transfer Level (RTL). The curriculum then guides you through the 'Backend' flow, where you will learn how to turn code into physical layouts, managing constraints like timing, power, and area. With a focus on industry-standard workflows including Static Timing Analysis (STA) and Physical Verification (DRC/LVS), this course prepares you for a career in the high-demand field of semiconductor engineering.

Duration

9-Week Program

Format

Expert-Led + LMS

Projects

6+ Live Projects

Certificate

Industry Verified

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Programs

About The Program

Master the complete chip design flow, from Digital Logic and Verilog coding to Physical Layout and Verification.

Digital Electronics & MOS Fundamentals

HDL Programming (Verilog/SystemVerilog)

RTL Design & Synthesis

Physical Design (Backend Flow)

Verification & Testing

Curriculum

Course Curriculum

Comprehensive learning path designed by industry experts

Module 1: Digital Electronics & MOS Fundamentals

2 weeks•6 lessons

Module 2: HDL Programming (Verilog/SystemVerilog)

2 weeks•6 lessons

Module 3: RTL Design & Synthesis

2 weeks•5 lessons

Module 4: Physical Design (Backend Flow)

2 weeks•5 lessons

Module 5: Verification & Testing

1 week•4 lessons

Projects

Hands-On Projects

Our Real-Time projects help you gain knowledge and enhance your skills.

Scroll horizontally to explore all projects.

8-bit ALU Design

Design and simulate an Arithmetic Logic Unit capable of performing addition, subtraction, and logical operations using Verilog.

Tech Stack

VerilogDigital LogicRTL

Tools

Xilinx VivadoModelSimGTKWave

Skills

RTL DesignCombinational LogicSimulation & Verification

Traffic Light Controller (FSM)

Implement a Finite State Machine (FSM) to control a traffic intersection, optimizing for timing and safety logic.

Tech Stack

VerilogFSMSystemVerilog

Tools

Xilinx VivadoModelSimSynopsys VCS

Skills

State Machine DesignSequential LogicTiming Analysis

RISC-V Processor Core

Build a simplified single-cycle RISC-V processor, understanding the data path and control unit architecture.

Tech Stack

VerilogRISC-V ISARTL

Tools

Xilinx VivadoRISC-V GNU ToolchainVerilator

Skills

Processor ArchitectureDatapath DesignControl Unit Logic

CMOS Inverter Layout

Create the physical layout of a CMOS inverter, performing DRC (Design Rule Check) and LVS (Layout vs. Schematic).

Tech Stack

CMOSSPICELayout Design

Tools

Cadence VirtuosoMagic VLSIHSPICE

Skills

Physical LayoutDRC/LVS VerificationTransistor Sizing

FIFO Memory Buffer

Design a First-In-First-Out memory buffer to manage data flow between different clock domains (Clock Domain Crossing).

Tech Stack

VerilogSystemVerilogRTL

Tools

Synopsys Design CompilerModelSimXilinx Vivado

Skills

Clock Domain CrossingMemory DesignFIFO Architecture

UART Communication Module

Develop a Universal Asynchronous Receiver-Transmitter (UART) protocol for serial communication between devices.

Tech Stack

VerilogUART ProtocolRTL

Tools

Xilinx VivadoModelSimTera Term

Skills

Serial Protocol DesignBaud Rate GenerationTestbench Writing

Certificates

CERTIFICATIONS

On completion of a program each participant gets a course completion, internship and outstanding performance certificates.

Course Completion Certificate

Awarded upon successful completion of the course curriculum.

Internship Certificate

Awarded after gaining practical work experience by successful completion of the capstone projects.

Outstanding Performance Certificate

Awarded to recognize exceptional performance and contributions during the program.

Partners

Training Partners

We collaborate with leading organizations to provide you with the best learning experience.